Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders

This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-ofproducts expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EXSOPs where some outputs of the function are minimized in the complemented form and presented techniques to minimize EX-SOPs for adders by using an extension of Dubrova-Miller-Muzio’s AOXMIN algorithm. The proposed algorithm produces solutions with a half products of AOXMINlike algorithm in 250 times shorter time for large adders with two-valued inputs. We also proved that an n-bit adder with two-valued inputs requires at most 3 · 2n−2 + 7n − 5 products in an EX-SOP while it is known that a sum-of-products expression (SOP) requires 6 · 2n − 4n − 5 products. key words: three-level network, logic minimization, adder, programmable logic